1. Technical Field
The disclosure relates generally to integrated circuit (IC) fabrication, and more particularly, to methods of forming a contact, and a related semiconductor device.
2. Background Art
As semiconductor devices have continually scaled to smaller sizes, e.g., below a 90 nm regime, major challenges arise relative to forming contacts to the devices. For example, shorting between a device's source/drain and the gate conductor due to the small space between gates is a problem. In addition, patterning smaller contacts presents a problem. More particularly, contact size and the alignment tolerance of a contact to a device cannot be scaled (miniaturized) at the same pace as the semiconductor device itself. FIG. 1 illustrates some of the problems. FIG. 1 shows a gate 10 and a contact hole 12 opened adjacent thereto, and a dielectric stress liner 14 (dark black line) for device performance enhancement. A sidewall 16 of gate 10 can be severely damaged when removing liner 14 from a bottom of contact hole 12. In particular, an upper corner 18 of gate 10 is very vulnerable during etching such that any over-etch to clean liner 14 may expose gate 10. Normally, however, in order to ensure proper formation of a small contact opening, certain over-etching is necessary. However, it is crucial to avoid damaging sidewall 16 of gate 10 during the etching.
One approach to address this situation is disclosed in US Patent Publication US2004/0092090A1 to Jae-Jung Han et al., which describes a method of forming a gate electrode. In this approach, after a gate structure is formed on a substrate, a first oxide film is formed on a sidewall of the gate structure and on the substrate by re-oxidizing the gate structure and the substrate under an atmosphere including an oxygen gas and an inert gas. The gate structure has a gate oxide film pattern, a polysilicon film pattern and a metal silicide film pattern. A portion of the first oxide film formed on a sidewall of the polysilicon film pattern has a thickness substantially identical to that of a portion of the first oxide film formed on a sidewall of the metal silicide film pattern. One issue with this approach is that when the devices are formed there is not much of a thermal budget left to allow thermal oxidation. Very shallow junctions are especially difficult to handle using this approach because the oxidation, even if done at very low temperature, could be detrimental to the junctions. In addition, since all the layers in this approach are formed before contact formation, i.e., none of the layers are formed after the contact hole is opened, there is no guarantee that this is a short-proof solution.
Another challenge is maintaining any intrinsic stress of liner 14 as it is pierced by the contacts. More particularly, the application of stresses to field effect transistors (FETs) is known to improve their performance. When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress is known to enhance electron mobility (or n-channel FET (NFET) drive currents) while compressive stress is known to enhance hole mobility (or p-channel FET (PFET) drive currents). One way to apply such stresses to a FET is the use of intrinsically-stressed liners, e.g., of silicon nitride (Si3N4). For example, a tensile-stressed silicon nitride liner may be used to cause tension in an NFET channel while a compressively-stressed silicon nitride liner may be used to cause compression in a PFET channel. Unfortunately, when the liner is punched with millions of holes for the contacts, the stress characteristic is greatly degraded. As a result, the effect of carrier mobility enhancement is also diminished and the device performance enhancement feature is lost.